Free NCP-AII Practice Test Questions 2026

Explanation

This question tests how new firmware is applied to a switch-attached transceiver without a service interruption. NVIDIA's MFT tooling separates transferring the firmware image from activating it. Activation is done through the flint utility using the LinkX options, so a full reset, a reboot, or physical handling of the module is not required.

✅ C. flint -d -lid 27 --linkx --linkx_auto_update --activate
This command uses flint with the --linkx option to target cables and transceivers connected to the switch. The --linkx_auto_update flag covers all supported modules, and --activate applies the already transferred firmware. Activation is not performed by default, so this step switches the module to the new image. It also includes a short built-in delay to avoid disconnections, and no reset or reboot is needed.

❌ A. mlxfwreset -d -lid 27 reset --yes to reset the transceiver
The mlxfwreset utility resets a device so that firmware loaded to it takes effect, and it is not the documented method for activating transceiver firmware. A reset disrupts the device and its links, which is the interruption the engineer wants to avoid. The flint --linkx workflow with --activate applies transceiver firmware without such a reset.

❌ B. Physically disconnect and reconnect the transceiver.
Unplugging and reseating a transceiver drops the link on that port, so it directly interrupts the network. It also does not install anything, because firmware must first be burned and transferred with flint. Physical handling adds risk and manual effort. The supported approach is to activate the new firmware remotely through software commands.

❌ D. nv action reboot system to force immediate activation.
Rebooting the entire switch forces every port and connected workload offline, so it is the most disruptive option. A system reboot is also not the documented way to activate transceiver firmware, which is done with the flint activate step. Rebooting adds downtime without any benefit over targeted activation, which avoids interrupting traffic.

Reference
🔧 Burning a Firmware Image – NVIDIA Firmware Tools (MFT) Documentation → confirms that flint with --linkx, --linkx_auto_update, and --activate applies new transceiver firmware, and that activation includes a short delay to avoid disconnections.

Explanation:

The question tests the standard way to launch a Docker container with full GPU access when the NVIDIA Container Toolkit is installed. The --gpus all flag is the modern, recommended method to expose all host GPUs to the container so that tools such as nvidia-smi work inside it.

✅ Correct Option: C. docker run --rm --gpus all nvidia/cuda:12.4.6-base-ubuntu22.04 nvidia-smi
This command uses the official --gpus all flag provided by the NVIDIA Container Toolkit. It starts a CUDA base image, grants access to every available GPU, and runs nvidia-smi to verify that the GPUs are visible and usable inside the container.

❌ Incorrect Option: A. docker run --rm --runtime=docker nvidia/cuda nvidia-smi
--runtime=docker is invalid and does not enable GPU support. The correct runtime is nvidia (or the default configured by the toolkit). This command will fail to expose any GPUs.

❌ Incorrect Option: B. docker run --rm -it ubuntu:22.04 nvidia-smi
A plain Ubuntu image does not include CUDA libraries or the NVIDIA runtime hooks. Without the --gpus flag (or equivalent), no GPUs are visible and nvidia-smi will not work.

❌ Incorrect Option: D. docker run --rm nvidia/cuda:12.4.0-base-ubuntu22.04 nvidia-smi
This command omits the --gpus flag entirely. Even though a CUDA image is used, the container has no access to the host GPUs, so nvidia-smi will report that no devices are found.

🔧 Reference:
→ Specialized Configurations with Docker – NVIDIA Container Toolkit
Confirms the canonical command docker run --rm --gpus all nvidia/cuda nvidia-smi for verifying GPU access.

Explanation:

The question tests the key hardware and infrastructure checks required before adding GPUs to an existing server. The system must provide compatible PCIe connectivity, sufficient electrical power, adequate cooling and airflow, and physical capacity for the additional hardware. NVIDIA's system configuration guidance emphasizes compatible GPU/PCIe configurations and balanced PCIe topology.

🟢 Correct Option:

D. Sufficient cooling in the data center, adequate rack power, compatible hardware, and PCIe slot allocation.
These are essential prerequisites for safely installing additional GPUs. The server must have compatible hardware and suitable PCIe slots with the required lanes, while the rack must provide enough power and cooling capacity for the increased GPU load. NVIDIA also emphasizes appropriate PCIe topology and airflow when configuring GPU servers.

🔴 Incorrect Options:

A. Sufficient networking, water-cooled racks, adequate rack power, sufficient storage, and rack space.
Networking and storage can be important for workloads, but they are not the primary prerequisites for physically adding GPUs. Requiring water-cooled racks is also unnecessarily specific because GPU servers can use different cooling designs.

B. Sufficient storage, sufficient networking, adequate rack power, and compatible hardware.
This includes power and hardware compatibility, but omits critical checks for PCIe slot availability and cooling capacity. Additional GPUs require appropriate PCIe connectivity and sufficient thermal capacity to operate safely.

C. Sufficient CPU capacity, PCIe slot allocation, sufficient cooling in the data center, and rack space.
These checks are relevant, but adequate rack power and GPU hardware compatibility are also essential. The option therefore leaves out two important requirements for safely and correctly installing additional GPUs.

🔧 Reference:
⇒ NVIDIA-Certified Systems Configuration Guide — Confirms GPU hardware compatibility, PCIe slot requirements, and appropriate PCIe topology for GPU servers.

⇒ NVIDIA DGX H100/H200 Safety and Rack Guidelines — Covers rack power, airflow, operating environment, and cooling considerations.

Explanation:

This question tests the root cause of inconsistent NCCL scaling in multi-GPU training. The performance issue stems from workload imbalance, which causes some GPUs to finish compute earlier than others and wait idle during collective synchronization.

✅ Correct Option:

A. Adjust the batch size so that each GPU receives an equal-sized portion of the batch, ensuring all GPUs process similar workloads and communication is evenly distributed.
NCCL collective operations are synchronous: every GPU must reach the same barrier before data exchange can complete. When workloads are unevenly distributed, faster GPUs sit idle waiting for slower ones, directly degrading scaling efficiency . Equalizing per-GPU batch sizes keeps all ranks synchronized and maximizes collective bandwidth utilization.

❌ Incorrect options:

B. Assign the largest possible workload to the first GPU to maximize its utilization, and allow the remaining GPUs to process smaller or variable batch sizes as needed.
This deliberately creates the imbalance causing the problem. NCCL synchronization requires all ranks to arrive at the collective together. Uneven workloads force faster GPUs to stall at synchronization points, wasting compute cycles .

C. Disable automatic load balancing so that the deep learning framework can dynamically assign samples to any GPU available during each iteration.
Disabling load balancing removes the mechanism that equalizes work across GPUs. This would worsen synchronization delays because NCCL collectives cannot proceed until every rank contributes its data, regardless of how samples were assigned.

D. Increase the communication frequency between GPUs while allowing workloads to be unevenly split, so synchronization is more frequent and model updates happen faster.
More frequent communication with uneven splits compounds the problem: each synchronization point becomes another idle-wait event for faster GPUs. Increasing communication frequency without fixing load balance amplifies the bottleneck rather than resolving it .

🔧 Reference:
→ NVIDIA NCCL Documentation – Tuning Overview
Explains that NCCL collective efficiency depends on balanced participation across ranks and that optimal tuning considers communicator dimensions and workload distribution.

Explanation:

This question tests your ability to troubleshoot InfiniBand physical and logical cabling errors using NVIDIA Unified Fabric Manager (UFM). A "Wrong-neighbor" error indicates a mismatch between the detected cable connectivity and the expected topology design.

✅ Correct Option:

✅ C. Verify LLDP data against topology files and remediate.
The UFM Cable Validation Tool compares real-time link discovery data, obtained via protocols like LLDP/SM, against the intended cluster topology configuration file. A "Wrong-neighbor" error means a cable is physically plugged into the wrong switch port or host HCA. Comparing detected neighbor data with the design plan identifies misconfigured cables so they can be re-routed correctly.

❌ Incorrect options:

❌ A. Reboot all leaf switches to force LLDP rediscovery.
Rebooting switches causes unnecessary cluster downtime and will not resolve physical cabling errors. While rediscovery runs after a reboot, the tool will continue reporting "Wrong-neighbor" errors as long as the physical connections do not match the expected topology file.

❌ B. Replace all affected cables with higher-grade OM5 fiber optics.
A "Wrong-neighbor" alert indicates a topological mapping error, not a hardware defect or signal degradation issue. Replacing functional cables with different fiber types is expensive, unnecessary, and fails to fix incorrectly wired port connections.

❌ D. Disable FEC on all switches to bypass neighbor validation.
Forward Error Correction (FEC) manages bit error rates on high-speed links and has no relation to topology validation or neighbor identification. Disabling FEC degrades link quality without resolving the underlying cabling misplacement.

🔧 Reference:
→ NVIDIA UFM Enterprise User Guide confirms how UFM validates physical cable connections against topology definition files.

Explanation

The question tests how NCCL test groups can be split to isolate traffic between two rack groups. Using MOD 2 divides ranks into two groups based on alternating rank values, allowing simultaneous collective operations across separate groups and isolating the intended East-West communication pattern.

✔️ Correct Option

C. NCCL_TESTS_SPLIT="MOD 2" ./all_reduce_perf -g 8
MOD 2 creates two NCCL test groups by assigning ranks according to their remainder after division by two. With eight GPUs, this produces two complementary groups that can represent the two rack sides in a controlled bisection test. Running all_reduce_perf with these split groups enables measurement of traffic crossing the rack boundary rather than mixing all communication paths.

❌ Incorrect Options

A. NCCL_TESTS_SPLIT="OR 0x7" ./all_reduce_perf -g 8
OR 0x7 groups ranks according to a bitwise OR operation and is documented for creating one operation per node with primarily intra-node communication. It does not form the two alternating groups required to isolate East-West traffic between racks.

B. Run without splits and analyze per-rack averages.
Without NCCL_TESTS_SPLIT, all ranks participate in the same collective operation. The resulting bandwidth includes a mixture of intra-rack and inter-rack paths, so per-rack averages cannot reliably isolate bisectional East-West bandwidth.

D. NCCL_TESTS_SPLIT="DIV 8" ./all_reduce_perf -g 1
DIV 8 is intended to create one group per node for intra-node communication, not two rack-level groups. Additionally, -g 1 runs only one GPU per process, which does not provide the eight-GPU test scope specified by the scenario.

🔧 Reference
→ NVIDIA HPC-X Bisectional Bandwidth Test
— Describes bisectional bandwidth testing for measuring communication across fabric partitions.

Explanation

This question tests how to prevent GPU out-of-memory errors in NeMo Curator when processing large datasets. Two things control this. The first is how much data is loaded per partition, set through the blocksize parameter. The second is how efficiently GPU memory is allocated, handled by RAPIDS Memory Manager (RMM) options. Together they cut memory pressure without sacrificing throughput.

✅ A. Set blocksize="1GB" for data loading and enable RMM asynchronous allocation.
Setting blocksize="1GB" keeps each loaded partition small, and NVIDIA recommends about 1/32 of GPU memory, which is 1 GB on a 32 GB GPU. Enabling RMM asynchronous allocation lets GPU memory be allocated and freed more efficiently, reducing fragmentation. Together, controlled partition size and better allocation prevent OOM errors during a long burn-in while keeping processing efficient.

❌ B. Switch from FP16 to FP32 precision for numerical stability.
FP32 stores each value in twice as many bytes as FP16, so it increases GPU memory use rather than reducing it. It may help numerical stability, but that is unrelated to the memory errors described. Moving to FP32 would make out-of-memory conditions more likely on large datasets, and it would also slow processing.

❌ C. Disable add_filename for Parquet files to reduce metadata.
Disabling add_filename is only a prerequisite: for Parquet files, blocksize is supported only when add_filename is False. By itself it saves a negligible amount of memory and does not limit how much data is loaded per partition. Without a suitable blocksize and memory allocation settings, OOM errors would continue.

❌ D. Increase files_per_partition to 1000 for larger batch processing.
Raising files_per_partition to 1000 loads far more data into each partition at once. Larger batches speed up processing at the cost of higher memory consumption, which makes OOM errors more likely, not less. To reduce memory load, the partition size should be lowered or capped with blocksize, not increased.

Reference
🔧 Best Practices for Data Curation – NVIDIA NeMo Framework User Guide (NVIDIA Docs) → confirms that blocksize (1/32 of GPU memory, e.g. 1GB on a 32GB GPU) and RMM asynchronous allocation help avoid OOM errors, and that blocksize on Parquet requires add_filename=False.

Explanation:

The question tests the most efficient GUI method in NVIDIA UFM for obtaining a consolidated view of transceiver firmware versions across many ports. UFM’s Devices window provides structured tables that surface cable and transceiver details without requiring per-port CLI commands or log parsing.

✅ Correct Option: A. Navigate to ’Devices" > select a switch > "Cables' tab to see ASIC firmware and transceiver versions.
Selecting a switch in the Devices window and opening the Cables tab displays a tabular list of all connected cables/transceivers for that device, including firmware versions. This gives an administrator a clear, consolidated per-switch view that can be repeated across switches to cover 200 ports efficiently.

❌ Incorrect Option: B. Use "Topology’ view to visually inspect cable icons.
The Topology (Network Map) view shows visual link icons and basic status but does not display detailed transceiver firmware version numbers in a usable consolidated table.

❌ Incorrect Option: C. Run mlxlink -d lid- -m on each port manually.
This is a command-line method that must be executed individually for every port. It is not GUI-based and does not scale to 200 ports.

❌ Incorrect Option: D. Export all switch logs and grep for ’FW Version".
Exporting and grepping logs is a manual, non-GUI process that is time-consuming and error-prone for large numbers of ports.

🔧 Reference:
→ Devices Window – NVIDIA UFM Enterprise User Manual
Documents the Cables tab under Device Information, which lists connected cables and their firmware versions.

Explanation:

The question tests the essential setup and validation steps for BCM head-node High Availability. A shared virtual IP provides a stable access point that follows the active head node, while a controlled failover test verifies that the secondary head node can assume the active role and that BCM services recover correctly.

🟢 Correct Option:

A. Assign a floating Virtual IP address that can automatically migrate between the primary and secondary head nodes during failover.
BCM HA uses a virtual shared IP address that represents the active head node. During failover, this address moves to the secondary node, allowing clients and administrators to continue accessing BCM through the same endpoint. NVIDIA's HA topology explicitly defines shared virtual interfaces and IP addresses for the internal and external networks.

C. After configuration is complete, simulate a failover by stopping BCM services on the active head node to verify that all services are running on the secondary node with no interruption.
A failover test is an important validation step after HA configuration. NVIDIA's deployment guidance recommends testing failover and verifying that the secondary becomes active, ensuring the HA configuration actually provides service continuity. This validates both failover behavior and access through the shared HA address before relying on the cluster in production.

🔴 Incorrect Options:

B. Compute nodes must be powered on and performing work to initiate synchronization of the head nodes.
Compute nodes do not need to be actively running workloads for head-node HA synchronization. HA setup and synchronization are performed between the head nodes, and NVIDIA documentation indicates that other nodes can be powered off during the basic HA setup.

D. Configure both head nodes to use independent static IP addresses for BCM services instead of relying on a shared virtual IP address.
Each head node does have its own node-specific addresses, but BCM HA also requires shared virtual addressing for services that must remain accessible after failover. Replacing the shared virtual IP with independent service addresses would undermine transparent failover.

E. During configuration, explicitly synchronize both the configuration and state data directories from the primary to the secondary head node to ensure consistency.
BCM's HA setup handles the necessary head-node cloning and synchronization through its HA configuration process. Manually synchronizing configuration and state directories is not the mandatory procedure described for establishing BCM head-node HA.

🔧 Reference:
⇒ NVIDIA Base Command Manager — High Availability — NVIDIA Base Command Manager — HA Concepts and Virtual Shared IP: documents the shared virtual IP and BCM head-node failover architecture.

⇒ NVIDIA Enterprise Reference Architectures — BCM HA Deployment Guide — NVIDIA Enterprise Reference Architectures — BCM HA Failover Testing: documents testing failover by making the secondary head node active and verifying continued access.

Explanation:

This question tests proper electrostatic discharge (ESD) precautions when handling sensitive electronic components like GPUs. ESD can permanently damage GPU circuitry, so grounding the technician is the essential safety measure.

✅ Correct Option:

A. Anti-ESD strap
An anti-ESD wrist strap grounds the technician to the server chassis, safely dissipating static electricity from the body before it can discharge into the GPU . Even small static discharges imperceptible to humans can destroy sensitive semiconductor components, making this the mandatory protective item during GPU installation.

❌ Incorrect options:

B. Gloves
Gloves are not a substitute for ESD protection and may actually increase static buildup depending on material. They do not provide the electrical grounding path required to safely dissipate static charge from the technician's body .

C. Protective film
Protective film is used for shipping and storage to protect components from physical damage, not for ESD prevention during installation. It offers no grounding function and is removed before the GPU is handled .

D. Electric screwdriver
An electric screwdriver is a convenience tool for fastening screws, not a safety device. It provides no ESD protection and, if improperly used, could overtighten screws or damage the GPU bracket .

🔧 Reference:
→ NVIDIA DGX SuperPOD – Safety and ESD Precautions
Confirms ESD wrist straps and grounded work surfaces are required when handling NVIDIA GPU hardware to prevent electrostatic damage.

→ NVIDIA DGX A100 User Guide – ESD Precautions
States that ESD straps must be worn when handling components and that static-dissipative materials are required for safe GPU installation.

Explanation

The question tests how to prevent GPU out-of-memory errors during NVIDIA HPL out-of-core execution. HPL_OOC_SAFE_SIZE reserves a specified amount of GPU memory for the driver and other system requirements, preventing HPL from consuming the entire GPU memory capacity.

✔️ Correct Option

A. export HPL_OOC_SAFE_SIZE=4.0
HPL_OOC_SAFE_SIZE defines the amount of GPU memory, measured in GiB, that the out-of-core HPL workload must leave available for the GPU driver. Setting it to 4.0 reserves 4 GiB and reduces the risk of out-of-memory failures during a large 40B matrix burn-in. NVIDIA recommends increasing this value when HPL OOC encounters GPU memory issues.

❌ Incorrect Options

B. export HPL_OOC_MODE=0
This disables HPL out-of-core mode. Because the matrix exceeds the available GPU memory, disabling OOC would prevent HPL from using host memory for excess matrix data and could cause allocation failure.

C. export HPL_OOC_NUM_STREAMS=8
This controls the number of streams used for out-of-core operations. More streams may affect overlap and performance, but the variable does not reserve GPU memory for drivers or directly prevent out-of-memory errors.

D. export HPL_OOC_MAX_GPU_MEM=90
This limits the GPU memory available to HPL OOC, but it is not the specific safety buffer intended to reserve memory for drivers. HPL_OOC_SAFE_SIZE directly defines the memory that HPL must leave unused for that purpose.

🔧 Reference
→ NVIDIA HPL Benchmark: Out-of-Core Mode
— Confirms that HPL_OOC_SAFE_SIZE reserves GPU memory for the driver and is used to address OOC memory errors.

→ NVIDIA Release Notes
— Recommends increasing HPL_OOC_SAFE_SIZE when HPL out-of-core execution reports GPU out-of-memory issues.

Explanation

This question tests how to connect ports with different form factors, here a 25 GbE SFP-based adapter and a QSFP port that supports both 100 GbE and 25 GbE. The QSFP cage has four lanes and the SFP port has one. A physical adapter is needed to bridge the two connector types while keeping the link at 25 GbE.

✅ A. QSA adapter.
A QSA (QSFP to SFP Adapter) installs into the QSFP port and provides an SFP receptacle. This lets an SFP28 transceiver or cable connect to the QSFP port and link at 25 GbE. It maps the single SFP lane to lane 1 of the QSFP connector. It is a passive, vendor-agnostic, plug-in solution, so no other equipment needs to change.

❌ B. SFP connectors.
"SFP connectors" is not a solution on its own, because the port in question is a QSFP cage, which physically cannot accept an SFP module or cable directly. An SFP connector is one side of the link, not something that bridges the two form factors. A QSA adapter is required to convert the QSFP port into an SFP-compatible receptacle.

❌ C. SFP-to-1G BASE-T RJ45 adapter.
An SFP-to-1G BASE-T RJ45 module converts an SFP port to a 1 Gb/s copper twisted-pair interface. It would cap the link at 1 GbE, far below the required 25 GbE, and it still would not fit into the QSFP cage. It solves a media conversion problem, not the SFP-to-QSFP form factor mismatch.

❌ D. Standard QSFP-to-QSFP DAC cable.
A QSFP-to-QSFP direct attach cable has QSFP connectors at both ends, so it can only connect two QSFP ports. It cannot plug into the SFP port on the 25 GbE adapter. It also carries four lanes and would not match the single-lane 25 GbE connection. Connecting a QSFP port to an SFP port needs a QSA adapter or a breakout cable.

Reference
🔧 MAM1Q00A-QSA NVIDIA DynamiX QSA™, QSFP+ to SFP+ Adapter Product Specifications → confirms that the QSA28 lets an SFP28 transceiver or cable connect to a QSFP28 port, joining a single-lane device to a quad-lane port.